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00071 #include <pkgconf/hal.h>
00072
00073 #include <cyg/hal/hal_io.h>
00074 #include <cyg/hal/hal_misc.h>
00075 #include <cyg/hal/hal_intr.h>
00076 #include <cyg/hal/hal_arch.h>
00077 #include <cyg/hal/hal_if.h>
00078 #include <cyg/hal/mod_regs_sci.h>
00079
00080 #include <cyg/hal/h8s_sci.h>
00081
00082
00083
00084
00085
00086 #if !defined(CYGPKG_KERNEL) || defined(CYGFUN_KERNEL_API_C)
00087 #include <cyg/hal/drv_api.h>
00088 #endif
00089
00090
00091
00092
00100
00101 void hal_sci_init_channel(void* chan)
00102 {
00103 cyg_uint8 tmp;
00104 cyg_uint8 *base = ((channel_data_t *)chan)->base;
00105
00106
00107
00108
00109
00110 HAL_WRITE_UINT8(base + _REG_SCSCR, CYGARC_REG_SCSCR_TE | CYGARC_REG_SCSCR_RE);
00111 HAL_WRITE_UINT8(base + _REG_SCSMR, 0);
00112 HAL_READ_UINT8(base + _REG_SCSMR, tmp);
00113 tmp &= ~CYGARC_REG_SCSMR_CKSx_MASK;
00114 tmp |= CYGARC_SCBRR_CKSx(((channel_data_t *)chan)->baud_rate);
00115 HAL_WRITE_UINT8(base + _REG_SCSMR, tmp);
00116 HAL_WRITE_UINT8(base + _REG_SCBRR, CYGARC_SCBRR_N(((channel_data_t *)chan)->baud_rate));
00117 }
00118
00119
00120
00121
00122
00132
00133 static cyg_bool hal_sci_getc_nonblock(void* __ch_data, cyg_uint8* ch)
00134 {
00135 cyg_uint8 *base = ((channel_data_t*)__ch_data)->base;
00136 cyg_uint8 sr;
00137
00138 HAL_READ_UINT8(base+ _REG_SCSSR, sr);
00139
00140
00141
00142 if (sr & CYGARC_REG_SCSSR_ORER)
00143 {
00144
00145
00146
00147 HAL_WRITE_UINT8(base + _REG_SCSSR,
00148 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER);
00149 return false;
00150 }
00151
00152
00153
00154 if ((sr & CYGARC_REG_SCSSR_RDRF) == 0)
00155 {
00156 return false;
00157 }
00158
00159
00160
00161 HAL_READ_UINT8(base+_REG_SCRDR, *ch);
00162 HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_RDRF);
00163
00164 return true;
00165 }
00166
00167
00168
00169
00175
00176 cyg_uint8 hal_sci_getc(void *__ch_data)
00177 {
00178 cyg_uint8 ch;
00179 CYGARC_HAL_SAVE_GP();
00180
00181 while(!hal_sci_getc_nonblock(__ch_data, &ch))
00182 {
00183
00184 }
00185
00186 CYGARC_HAL_RESTORE_GP();
00187 return ch;
00188 }
00189
00190
00191
00192
00202
00203 void hal_sci_putc(void *__ch_data, cyg_uint8 c)
00204 {
00205 cyg_uint8 *base = ((channel_data_t*)__ch_data)->base;
00206 cyg_uint8 sr;
00207
00208
00209 CYGARC_HAL_SAVE_GP();
00210
00211
00212
00213 do
00214 {
00215 HAL_READ_UINT8(base + _REG_SCSSR, sr);
00216 }
00217 while ((sr & CYGARC_REG_SCSSR_TDRE) == 0);
00218
00219
00220
00221 HAL_WRITE_UINT8(base + _REG_SCTDR, c);
00222 HAL_WRITE_UINT8(base + _REG_SCSSR, sr & ~CYGARC_REG_SCSSR_TDRE);
00223
00224
00225
00226 do
00227 {
00228 HAL_READ_UINT8(base + _REG_SCSSR, sr);
00229 }
00230 while ((sr & CYGARC_REG_SCSSR_TDRE) == 0);
00231
00232 CYGARC_HAL_RESTORE_GP();
00233 }
00234
00235
00236
00237
00238
00239 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
00240
00241
00242
00250
00251 void hal_sci_write(void *__ch_data,
00252 const cyg_uint8 *__buf,
00253 cyg_uint32 __len)
00254 {
00255 CYGARC_HAL_SAVE_GP();
00256
00257
00258
00259 while(__len-- > 0)
00260 {
00261 hal_sci_putc(__ch_data, *__buf++);
00262 }
00263
00264 CYGARC_HAL_RESTORE_GP();
00265 }
00266
00267
00268
00269
00270
00279
00280 void hal_sci_read(void *__ch_data,
00281 cyg_uint8 *__buf,
00282 cyg_uint32 __len)
00283 {
00284 CYGARC_HAL_SAVE_GP();
00285
00286
00287
00288
00289 while(__len-- > 0)
00290 {
00291 *__buf++ = hal_sci_getc(__ch_data);
00292 }
00293
00294 CYGARC_HAL_RESTORE_GP();
00295 }
00296
00297
00298
00299
00307
00308 cyg_bool hal_sci_getc_timeout(void *__ch_data, cyg_uint8 *ch)
00309 {
00310 channel_data_t *chan = (channel_data_t*)__ch_data;
00311 int delay_count;
00312 cyg_bool res;
00313
00314
00315 CYGARC_HAL_SAVE_GP();
00316
00317 delay_count = chan->msec_timeout * 20;
00318
00319
00320
00321 while (1)
00322 {
00323 res = hal_sci_getc_nonblock(__ch_data, ch);
00324 if (res || (0 == delay_count--))
00325 {
00326 break;
00327 }
00328
00329 CYGACC_CALL_IF_DELAY_US(50);
00330 }
00331
00332 CYGARC_HAL_RESTORE_GP();
00333 return res;
00334 }
00335
00336
00337
00338
00355
00356 int hal_sci_control(void *__ch_data, __comm_control_cmd_t __func, ...)
00357 {
00358 channel_data_t *chan = (channel_data_t*)__ch_data;
00359 cyg_uint8 scr;
00360 int ret = 0;
00361
00362
00363 CYGARC_HAL_SAVE_GP();
00364
00365
00366
00367 switch (__func)
00368 {
00369
00370
00371
00372 case __COMMCTL_IRQ_ENABLE:
00373 HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
00374 scr |= CYGARC_REG_SCSCR_RIE;
00375 HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
00376 break;
00377
00378
00379
00380 case __COMMCTL_IRQ_DISABLE:
00381 HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
00382 scr &= ~CYGARC_REG_SCSCR_RIE;
00383 HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
00384 break;
00385
00386
00387
00388 case __COMMCTL_DBG_ISR_VECTOR:
00389 ret = chan->isr_vector;
00390 break;
00391
00392
00393
00394 case __COMMCTL_SET_TIMEOUT:
00395 {
00396 va_list ap;
00397
00398 va_start(ap, __func);
00399
00400 ret = chan->msec_timeout;
00401 chan->msec_timeout = va_arg(ap, cyg_uint32);
00402
00403 va_end(ap);
00404 }
00405 break;
00406
00407
00408
00409 case __COMMCTL_SETBAUD:
00410 {
00411 cyg_uint32 baud_rate;
00412 cyg_uint8 tmp;
00413 va_list ap;
00414
00415
00416
00417 va_start(ap, __func);
00418 baud_rate = va_arg(ap, cyg_uint32);
00419 va_end(ap);
00420
00421
00422
00423 HAL_READ_UINT8(chan->base + _REG_SCSCR, scr);
00424 tmp = scr;
00425 tmp = scr & ~(CYGARC_REG_SCSCR_TIE
00426 | CYGARC_REG_SCSCR_RIE
00427 | CYGARC_REG_SCSCR_MPIE
00428 | CYGARC_REG_SCSCR_TEIE);
00429 HAL_WRITE_UINT8(chan->base + _REG_SCSCR, tmp);
00430
00431
00432
00433 HAL_READ_UINT8(chan->base + _REG_SCSMR, tmp);
00434 tmp &= ~CYGARC_REG_SCSMR_CKSx_MASK;
00435 tmp |= CYGARC_SCBRR_CKSx(baud_rate);
00436 HAL_WRITE_UINT8(chan->base + _REG_SCSMR, tmp);
00437 HAL_WRITE_UINT8(chan->base + _REG_SCBRR, CYGARC_SCBRR_N(baud_rate));
00438
00439
00440
00441 HAL_WRITE_UINT8(chan->base + _REG_SCSCR, scr);
00442 }
00443 break;
00444
00445
00446
00447 case __COMMCTL_GETBAUD:
00448 break;
00449
00450
00451
00452 default:
00453 ;
00454 }
00455
00456 CYGARC_HAL_RESTORE_GP();
00457 return ret;
00458 }
00459
00460
00461
00462
00480
00481 int hal_sci_isr(void *__ch_data,
00482 int *__ctrlc,
00483 CYG_ADDRWORD __vector,
00484 CYG_ADDRWORD __data)
00485 {
00486 cyg_uint8 c;
00487 cyg_uint8 sr;
00488 cyg_uint8 *base = ((channel_data_t*)__ch_data)->base;
00489 int res = 0;
00490
00491
00492 CYGARC_HAL_SAVE_GP();
00493
00494 *__ctrlc = 0;
00495 HAL_READ_UINT8(base + _REG_SCSSR, sr);
00496 if (sr & CYGARC_REG_SCSSR_ORER)
00497 {
00498
00499
00500
00501 HAL_WRITE_UINT8(base+_REG_SCSSR,
00502 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER);
00503 res = CYG_ISR_HANDLED;
00504 }
00505 else if (sr & CYGARC_REG_SCSSR_RDRF)
00506 {
00507
00508 HAL_READ_UINT8(base+_REG_SCRDR, c);
00509 HAL_WRITE_UINT8(base+_REG_SCSSR,
00510 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
00511
00512 if(cyg_hal_is_break(&c, 1 ))
00513 {
00514 *__ctrlc = 1;
00515 }
00516
00517 res = CYG_ISR_HANDLED;
00518 }
00519
00520 CYGARC_HAL_RESTORE_GP();
00521 return res;
00522 }
00523 #endif // End of #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
00524
00525
00526