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var_misc.c

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00001 //==========================================================================
00002 //
00003 //      var_misc.c
00004 //
00005 //      HAL CPU variant miscellaneous functions
00006 //
00007 //==========================================================================
00008 //####ECOSGPLCOPYRIGHTBEGIN####
00009 // -------------------------------------------
00010 // This file is part of eCos, the Embedded Configurable Operating System.
00011 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
00012 //
00013 // eCos is free software; you can redistribute it and/or modify it under
00014 // the terms of the GNU General Public License as published by the Free
00015 // Software Foundation; either version 2 or (at your option) any later version.
00016 //
00017 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
00018 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
00019 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
00020 // for more details.
00021 //
00022 // You should have received a copy of the GNU General Public License along
00023 // with eCos; if not, write to the Free Software Foundation, Inc.,
00024 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
00025 //
00026 // As a special exception, if other files instantiate templates or use macros
00027 // or inline functions from this file, or you compile this file and link it
00028 // with other works to produce a work based on this file, this file does not
00029 // by itself cause the resulting work to be covered by the GNU General Public
00030 // License. However the source code for this file must still be made available
00031 // in accordance with section (3) of the GNU General Public License.
00032 //
00033 // This exception does not invalidate any other reasons why a work based on
00034 // this file might be covered by the GNU General Public License.
00035 //
00036 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
00037 // at http://sources.redhat.com/ecos/ecos-license/
00038 // -------------------------------------------
00039 //####ECOSGPLCOPYRIGHTEND####
00040 //==========================================================================
00041 //#####DESCRIPTIONBEGIN####
00042 //
00043 // Author(s):    ysato
00044 // Contributors: ysato, Uwe Kindler
00045 // Date:         2003-12-06
00046 // Purpose:      HAL miscellaneous functions
00047 // Description:  This file contains miscellaneous functions provided by the
00048 //               HAL.
00049 //
00050 //####DESCRIPTIONEND####
00051 //
00052 //==========================================================================
00053 
00054 
00055 //==========================================================================
00056 //                            DOXYGEN FILE HEADER
00063 //==========================================================================
00064 
00065 
00066 //==========================================================================
00067 //                                 INCLUDES
00068 //==========================================================================
00069 #include <pkgconf/hal.h>
00070 
00071 #include <cyg/infra/cyg_type.h>         // Base types
00072 #include <cyg/infra/cyg_trac.h>         // tracing macros
00073 #include <cyg/infra/cyg_ass.h>          // assertion macros
00074 #include <cyg/hal/var_arch.h>
00075 #include <cyg/hal/var_intr.h>
00076 #include <cyg/hal/hal_intr.h>
00077 #include <cyg/hal/hal_io.h>
00078 
00079 
00080 //==========================================================================
00081 //                          VARIANT INITIALIZATION
00084 //==========================================================================
00085 void hal_variant_init(void)
00086 {
00087     // Nothing to do here at the moment
00088 }
00089 
00090 
00091 //==========================================================================
00092 //                     INTERRUPT REGISTER CONFIGURATION
00093 // DESCRIPTION:
00094 //     The following declarations and defines are required
00095 //==========================================================================
00096 
00097 //--------------------------------------------------------------------------
00104 typedef struct {
00105     cyg_uint8 prio_reg_no    : 5; 
00106     cyg_uint8 prio_bit_group : 3; 
00107 } int_prio_conf_t;
00108 
00109 
00110 //--------------------------------------------------------------------------
00111 // Priority bit group values for prio_bit_group member of hal_int_reg_conf
00112 //
00113 #define PRIO_14_TO_12   3
00114 #define PRIO_10_TO_08   2
00115 #define PRIO_06_TO_04   1
00116 #define PRIO_02_TO_00   0
00117 
00118 
00119 //--------------------------------------------------------------------------
00126 static const cyg_uint32 hal_prio_reg_tbl[] =
00127 {
00128     CYGARC_IPRA,
00129     CYGARC_IPRB,
00130     CYGARC_IPRC,
00131     CYGARC_IPRD,
00132     CYGARC_IPRE,
00133     CYGARC_IPRF,
00134     CYGARC_IPRG,
00135     CYGARC_IPRH,
00136     CYGARC_IPRI,
00137     CYGARC_IPRJ,
00138     CYGARC_IPRK,
00139     0                
00140 };
00141 
00142 
00143 //--------------------------------------------------------------------------
00144 // These macros simplify entries into hal_int_prio_conf_tbl[]
00145 //
00146 #define PRIO_CONF_TBL_ENTRY(_prio_reg_no_, _bit_group_) {(_prio_reg_no_), (_bit_group_)}
00147 #define IPR(_no_) ((_no_) - 'A')
00148 #define IPR_NONE  11                // last entry in hal_prio_reg_tbl
00149 
00150 
00151 //--------------------------------------------------------------------------
00156 static const int_prio_conf_t hal_int_prio_conf_tbl[CYGNUM_HAL_ISR_COUNT] = 
00157 {
00158     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 000  RSV
00159     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 001  RSV
00160     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 002  RSV
00161     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 003  RSV
00162     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 004  RSV
00163     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 005  RSV
00164     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 006  RSV
00165     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 007  NMI
00166     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 008  RSV
00167     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 009  RSV
00168     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 010  RSV
00169     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 011  RSV
00170     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 012  RSV
00171     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 013  RSV
00172     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 014  RSV
00173     PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 015  RSV
00174     PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_14_TO_12), // 016  IRQ 0
00175     PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_10_TO_08), // 017  IRQ 1
00176     PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_06_TO_04), // 018  IRQ 2
00177     PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_02_TO_00), // 019  IRQ 3
00178     PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_14_TO_12), // 020  IRQ 4
00179     PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_10_TO_08), // 021  IRQ 5
00180     PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_06_TO_04), // 022  IRQ 6
00181     PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_02_TO_00), // 023  IRQ 7
00182     PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_14_TO_12), // 024  IRQ 8
00183     PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_10_TO_08), // 025  IRQ 9
00184     PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_06_TO_04), // 026  IRQ 10
00185     PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_02_TO_00), // 027  IRQ 11
00186     PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_14_TO_12), // 028  IRQ 12
00187     PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_10_TO_08), // 029  IRQ 13
00188     PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_06_TO_04), // 030  IRQ 14
00189     PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_02_TO_00), // 031  IRQ 15
00190 
00191     //---------------------------------------------------------------------------------
00192     //
00193     //
00194     PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_14_TO_12), // 032  SWDTEND
00195     PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_10_TO_08), // 033  WOVI
00196     PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_06_TO_04), // 034  RSV
00197     PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_02_TO_00), // 035  CMI
00198     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_14_TO_12), // 036  RSV
00199     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_14_TO_12), // 037  RSV
00200     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_10_TO_08), // 038  ADI
00201     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_10_TO_08), // 039  RSV
00202     
00203     //---------------------------------------------------------------------------------
00204     // TPU 0
00205     //
00206     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 040  TGI0A
00207     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 041  TGI0B
00208     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 042  TGI0C
00209     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 043  TGI0D
00210     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 044  TCI0V
00211     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 045  RSV
00212     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 046  RSV
00213     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 047  RSV
00214 
00215     //---------------------------------------------------------------------------------
00216     // TPU 1
00217     //
00218     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 048  TGI1A
00219     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 049  TGI1B
00220     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 050  TCI1V
00221     PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 051  TCI1U
00222     
00223     //---------------------------------------------------------------------------------
00224     // TPU 2
00225     //
00226     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 052  TGI2A
00227     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 053  TGI2B
00228     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 054  TCI2V
00229     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 055  TCI2U
00230     
00231     //---------------------------------------------------------------------------------
00232     // TPU 3
00233     //
00234     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 056  TGI3A
00235     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 057  TGI3B
00236     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 058  TGI3C
00237     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 059  TGI3D
00238     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 060  TCI3V
00239     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 061  RSV
00240     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 062  RSV
00241     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 063  RSV
00242     
00243     //---------------------------------------------------------------------------------
00244     // TPU 4
00245     //
00246     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 064  TGI4A 
00247     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 065  TGI4B
00248     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 066  TCI4V
00249     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 067  TCI4U
00250 
00251     //---------------------------------------------------------------------------------
00252     // TPU 5
00253     //
00254     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 068  TGI5A
00255     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 069  TGI5B
00256     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 070  TCI5V
00257     PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 071  TCI5U
00258     
00259     //---------------------------------------------------------------------------------
00260     // TMR 0
00261     //
00262     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 072  CMIA0
00263     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 073  CMIB0
00264     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 074  OVI0
00265     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 075  RSV
00266     
00267     //---------------------------------------------------------------------------------
00268     // TMR 1
00269     //
00270     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 076  CMIA1
00271     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 077  CMIB1
00272     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 078  OVI1
00273     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 079  RSV
00274     
00275     //---------------------------------------------------------------------------------
00276     // DMAC
00277     //
00278     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 080  DMTEND0A
00279     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 081  DMTEND0B
00280     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 082  DMTEND1A
00281     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 083  DMTEND1B
00282     
00283     //---------------------------------------------------------------------------------
00284     // EXDMAC
00285     //
00286     PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_02_TO_00), // 084  EXDMTEND0A
00287     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_14_TO_12), // 085  EXDMTEND0B
00288     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_10_TO_08), // 086  EXDMTEND1A
00289     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_06_TO_04), // 087  EXDMTEND1B
00290 
00291     //---------------------------------------------------------------------------------
00292     // SCI 0
00293     //
00294     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 088  ERI0
00295     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 089  RXI0
00296     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 090  TXI0
00297     PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 091  TEI0
00298 
00299     //---------------------------------------------------------------------------------
00300     // SCI 1
00301     //
00302     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 092  ERI1
00303     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 093  RXI1
00304     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 094  TXI1
00305     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 095  TEI1
00306 
00307     //---------------------------------------------------------------------------------
00308     // SCI 2
00309     //
00310     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 096  ERI2
00311     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 097  RXI2
00312     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 098  TXI2
00313     PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 099  TEI2
00314 }; 
00315 
00316 //--------------------------------------------------------------------------
00322 cyg_uint8 hal_int_prio_tbl[CYGNUM_HAL_ISR_COUNT] =
00323 { 
00324     7, 7, 7, 7, 7, 7, 7, 7,   7, 7, 7, 7, 7, 7, 7, 7,
00325     7, 7, 7, 7, 7, 7, 7, 7,   7, 7, 7, 7, 7, 7, 7, 7,
00326     7, 7, 7, 7, 7, 7, 7, 7,   7, 7, 7, 7, 7, 7, 7, 7,
00327     7, 7, 7, 7, 7, 7, 7, 7,   7, 7, 7, 7, 7, 7, 7, 7,
00328     7, 7, 7, 7, 7, 7, 7, 7,   7, 7, 7, 7, 7, 7, 7, 7,
00329     7, 7, 7, 7, 7, 7, 7, 7,   7, 7, 7, 7, 7, 7, 7, 7,
00330     7, 7, 7, 7
00331 }; 
00332 
00333 
00334 //===========================================================================
00335 //                       INTERRUPT ACKNOWLEDGE TABLE
00336 // DESCRIPTION:
00337 //     This table contains all H8S/2674 interrupt status registers and the
00338 //     masks required for acknowledging the interrupt
00339 //===========================================================================
00343 typedef struct
00344 {
00345     cyg_uint32 mask    :  8;  
00346     cyg_uint32 address : 24;  
00347 } int_ackn_t;
00348 
00349 //
00350 // Use this macro when entering entries into the hal_int_mask_tbl. We store the
00351 // masks here so we do no need to do a not operation during runtime
00352 // 
00353 #define ACKN_TBL_ENTRY(_int_status_reg_, _mask_) {(_mask_), (_int_status_reg_)}
00354 #define CLR_BIT(_no_) ((cyg_uint8)(~(1 << (_no_))))
00355 
00361 const int_ackn_t hal_int_ackn_tbl[CYGNUM_HAL_ISR_COUNT] = 
00362 {
00363     ACKN_TBL_ENTRY(0,            0),          // 000  RSV
00364     ACKN_TBL_ENTRY(0,            0),          // 001  RSV
00365     ACKN_TBL_ENTRY(0,            0),          // 002  RSV
00366     ACKN_TBL_ENTRY(0,            0),          // 003  RSV
00367     ACKN_TBL_ENTRY(0,            0),          // 004  RSV
00368     ACKN_TBL_ENTRY(0,            0),          // 005  RSV
00369     ACKN_TBL_ENTRY(0,            0),          // 006  RSV
00370     ACKN_TBL_ENTRY(0,            0),          // 007  NMI
00371     ACKN_TBL_ENTRY(0,            0),          // 008  RSV
00372     ACKN_TBL_ENTRY(0,            0),          // 009  RSV
00373     ACKN_TBL_ENTRY(0,            0),          // 010  RSV
00374     ACKN_TBL_ENTRY(0,            0),          // 011  RSV
00375     ACKN_TBL_ENTRY(0,            0),          // 012  RSV
00376     ACKN_TBL_ENTRY(0,            0),          // 013  RSV
00377     ACKN_TBL_ENTRY(0,            0),          // 014  RSV
00378     ACKN_TBL_ENTRY(0,            0),          // 015  RSV
00379     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(0)), // 016  IRQ 0
00380     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(1)), // 017  IRQ 1
00381     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(2)), // 018  IRQ 2
00382     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(3)), // 019  IRQ 3
00383     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(4)), // 020  IRQ 4
00384     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(5)), // 021  IRQ 5
00385     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(6)), // 022  IRQ 6
00386     ACKN_TBL_ENTRY(CYGARC_ISRL,  CLR_BIT(7)), // 023  IRQ 7
00387     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(0)), // 024  IRQ 8
00388     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(1)), // 025  IRQ 9
00389     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(2)), // 026  IRQ 10
00390     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(3)), // 027  IRQ 11
00391     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(4)), // 028  IRQ 12
00392     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(5)), // 029  IRQ 13
00393     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(6)), // 030  IRQ 14
00394     ACKN_TBL_ENTRY(CYGARC_ISRH,  CLR_BIT(7)), // 031  IRQ 15
00395 
00396     //---------------------------------------------------------------------------------
00397     //
00398     //
00399     ACKN_TBL_ENTRY(0,            0),          // 032  SWDTEND
00400     ACKN_TBL_ENTRY(CYGARC_TCSRR, CLR_BIT(7)), // 033  WOVI
00401     ACKN_TBL_ENTRY(0,            0),          // 034  RSV
00402     ACKN_TBL_ENTRY(CYGARC_REFCRH,CLR_BIT(7)), // 035  CMI
00403     ACKN_TBL_ENTRY(0,            0),          // 036  RSV
00404     ACKN_TBL_ENTRY(0,            0),          // 037  RSV
00405     ACKN_TBL_ENTRY(CYGARC_ADCSR, CLR_BIT(7)), // 038  ADI
00406     ACKN_TBL_ENTRY(0,            0),          // 039  RSV
00407     
00408     //---------------------------------------------------------------------------------
00409     // TPU 0
00410     //
00411     ACKN_TBL_ENTRY(CYGARC_TSR0,  CLR_BIT(0)), // 040  TGI0A
00412     ACKN_TBL_ENTRY(CYGARC_TSR0,  CLR_BIT(1)), // 041  TGI0B
00413     ACKN_TBL_ENTRY(CYGARC_TSR0,  CLR_BIT(2)), // 042  TGI0C
00414     ACKN_TBL_ENTRY(CYGARC_TSR0,  CLR_BIT(3)), // 043  TGI0D
00415     ACKN_TBL_ENTRY(CYGARC_TSR0,  CLR_BIT(4)), // 044  TCI0V
00416     ACKN_TBL_ENTRY(0,            0),          // 045  RSV
00417     ACKN_TBL_ENTRY(0,            0),          // 046  RSV
00418     ACKN_TBL_ENTRY(0,            0),          // 047  RSV
00419 
00420     //---------------------------------------------------------------------------------
00421     // TPU 1
00422     //
00423     ACKN_TBL_ENTRY(CYGARC_TSR1,  CLR_BIT(0)), // 048  TGI1A
00424     ACKN_TBL_ENTRY(CYGARC_TSR1,  CLR_BIT(1)), // 049  TGI1B
00425     ACKN_TBL_ENTRY(CYGARC_TSR1,  CLR_BIT(4)), // 050  TCI1V
00426     ACKN_TBL_ENTRY(CYGARC_TSR1,  CLR_BIT(5)), // 051  TCI1U
00427     
00428     //---------------------------------------------------------------------------------
00429     // TPU 2
00430     //
00431     ACKN_TBL_ENTRY(CYGARC_TSR2,  CLR_BIT(0)), // 052  TGI2A
00432     ACKN_TBL_ENTRY(CYGARC_TSR2,  CLR_BIT(1)), // 053  TGI2B
00433     ACKN_TBL_ENTRY(CYGARC_TSR2,  CLR_BIT(4)), // 054  TCI2V
00434     ACKN_TBL_ENTRY(CYGARC_TSR2,  CLR_BIT(5)), // 055  TCI2U
00435     
00436     //---------------------------------------------------------------------------------
00437     // TPU 3
00438     //
00439     ACKN_TBL_ENTRY(CYGARC_TSR3,  CLR_BIT(0)), // 056  TGI3A
00440     ACKN_TBL_ENTRY(CYGARC_TSR3,  CLR_BIT(1)), // 057  TGI3B
00441     ACKN_TBL_ENTRY(CYGARC_TSR3,  CLR_BIT(2)), // 058  TGI3C
00442     ACKN_TBL_ENTRY(CYGARC_TSR3,  CLR_BIT(3)), // 059  TGI3D
00443     ACKN_TBL_ENTRY(CYGARC_TSR3,  CLR_BIT(4)), // 060  TCI3V
00444     ACKN_TBL_ENTRY(0,            0),      // 061  RSV
00445     ACKN_TBL_ENTRY(0,            0),      // 062  RSV
00446     ACKN_TBL_ENTRY(0,            0),      // 063  RSV
00447     
00448     //---------------------------------------------------------------------------------
00449     // TPU 4
00450     //
00451     ACKN_TBL_ENTRY(CYGARC_TSR4,  CLR_BIT(0)), // 064  TGI4A 
00452     ACKN_TBL_ENTRY(CYGARC_TSR4,  CLR_BIT(1)), // 065  TGI4B
00453     ACKN_TBL_ENTRY(CYGARC_TSR4,  CLR_BIT(4)), // 066  TCI4V
00454     ACKN_TBL_ENTRY(CYGARC_TSR4,  CLR_BIT(5)), // 067  TCI4U
00455 
00456     //---------------------------------------------------------------------------------
00457     // TPU 5
00458     //
00459     ACKN_TBL_ENTRY(CYGARC_TSR5,  CLR_BIT(0)), // 068  TGI5A
00460     ACKN_TBL_ENTRY(CYGARC_TSR5,  CLR_BIT(1)), // 069  TGI5B
00461     ACKN_TBL_ENTRY(CYGARC_TSR5,  CLR_BIT(4)), // 070  TCI5V
00462     ACKN_TBL_ENTRY(CYGARC_TSR5,  CLR_BIT(5)), // 071  TCI5U
00463     
00464     //---------------------------------------------------------------------------------
00465     // TMR 0
00466     //
00467     ACKN_TBL_ENTRY(CYGARC_8TCSR0,CLR_BIT(6)), // 072  CMIA0
00468     ACKN_TBL_ENTRY(CYGARC_8TCSR0,CLR_BIT(7)), // 073  CMIB0
00469     ACKN_TBL_ENTRY(CYGARC_8TCSR0,CLR_BIT(5)), // 074  OVI0
00470     ACKN_TBL_ENTRY(0,            0),      // 075  RSV
00471     
00472     //---------------------------------------------------------------------------------
00473     // TMR 1
00474     //
00475     ACKN_TBL_ENTRY(CYGARC_8TCSR1,CLR_BIT(6)), // 076  CMIA1
00476     ACKN_TBL_ENTRY(CYGARC_8TCSR1,CLR_BIT(7)), // 077  CMIB1
00477     ACKN_TBL_ENTRY(CYGARC_8TCSR1,CLR_BIT(5)), // 078  OVI1
00478     ACKN_TBL_ENTRY(0,            0),      // 079  RSV
00479     
00480     //---------------------------------------------------------------------------------
00481     // DMAC
00482     //
00483     ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(4)), // 080  DMTEND0A
00484     ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(5)), // 081  DMTEND0B
00485     ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(6)), // 082  DMTEND1A
00486     ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(7)), // 083  DMTEND1B
00487     
00488     //---------------------------------------------------------------------------------
00489     // EXDMAC
00490     //
00491     ACKN_TBL_ENTRY(CYGARC_EDMDR0L, CLR_BIT(6)), // 084  EXDMTEND0A
00492     ACKN_TBL_ENTRY(CYGARC_EDMDR1L, CLR_BIT(6)), // 085  EXDMTEND0B
00493     ACKN_TBL_ENTRY(CYGARC_EDMDR2L, CLR_BIT(6)), // 086  EXDMTEND1A
00494     ACKN_TBL_ENTRY(CYGARC_EDMDR3L, CLR_BIT(6)), // 087  EXDMTEND1B
00495 
00496     //---------------------------------------------------------------------------------
00497     // SCI 0
00498     //
00499     ACKN_TBL_ENTRY(CYGARC_SSR0,  CLR_BIT(3) & CLR_BIT(4) & CLR_BIT(5)), // 088  ERI0
00500     ACKN_TBL_ENTRY(CYGARC_SSR0,  CLR_BIT(6)), // 089  RXI0
00501     ACKN_TBL_ENTRY(CYGARC_SSR0,  CLR_BIT(7)), // 090  TXI0
00502     ACKN_TBL_ENTRY(CYGARC_SSR0,  CLR_BIT(2)), // 091  TEI0
00503 
00504     //---------------------------------------------------------------------------------
00505     // SCI 1
00506     //
00507     ACKN_TBL_ENTRY(CYGARC_SSR1,  CLR_BIT(3) & CLR_BIT(4) & CLR_BIT(5)), // 092  ERI1
00508     ACKN_TBL_ENTRY(CYGARC_SSR1,  CLR_BIT(6)), // 093  RXI1
00509     ACKN_TBL_ENTRY(CYGARC_SSR1,  CLR_BIT(7)), // 094  TXI1
00510     ACKN_TBL_ENTRY(CYGARC_SSR1,  CLR_BIT(2)), // 095  TEI1
00511 
00512     //---------------------------------------------------------------------------------
00513     // SCI 2
00514     //
00515     ACKN_TBL_ENTRY(CYGARC_SSR2,  CLR_BIT(3) & CLR_BIT(4) & CLR_BIT(5)), // 096 ERI2
00516     ACKN_TBL_ENTRY(CYGARC_SSR2,  CLR_BIT(6)), // 097  RXI2
00517     ACKN_TBL_ENTRY(CYGARC_SSR2,  CLR_BIT(7)), // 098  TXI2
00518     ACKN_TBL_ENTRY(CYGARC_SSR2,  CLR_BIT(2))  // 099  TEI2
00519 }; 
00520 
00521 
00522 //===========================================================================
00523 //                            INTERRUPT MASK TABLE
00524 // DESCRIPTION:
00525 //     This table contains all H8S/2674 interrupt enable registers and the
00526 //     masks required for masking or unmasking an interrupt
00527 //===========================================================================
00531 typedef struct
00532 {
00533     cyg_uint32 mask    :  8;   
00534     cyg_uint32 address : 24;   
00535 } int_mask_t;
00536 
00537 //
00538 // Use this macro when entering entries into the hal_int_mask_tbl
00539 // 
00540 #define MASK_TBL_ENTRY(_int_en_reg_, _mask_) {(_mask_), (_int_en_reg_)}
00541 #define BIT(_no_) ((_no_))
00542 //
00543 // this define should be used for interrupt vectors without a mask
00544 // register - i.e the NMI interrupt. This marks the interrupt as
00545 // available because not available interrupts contain a 0
00546 //
00547 #define NO_MASK_REG 1
00548 
00549 
00555 const int_mask_t hal_int_mask_tbl[CYGNUM_HAL_ISR_COUNT] =
00556 {
00557     MASK_TBL_ENTRY(0,            0),      // 000  RSV
00558     MASK_TBL_ENTRY(0,            0),      // 001  RSV
00559     MASK_TBL_ENTRY(0,            0),      // 002  RSV
00560     MASK_TBL_ENTRY(0,            0),      // 003  RSV
00561     MASK_TBL_ENTRY(0,            0),      // 004  RSV
00562     MASK_TBL_ENTRY(0,            0),      // 005  RSV
00563     MASK_TBL_ENTRY(0,            0),      // 006  RSV
00564     MASK_TBL_ENTRY(NO_MASK_REG,  0),      // 007  NMI
00565     MASK_TBL_ENTRY(0,            0),      // 008  RSV
00566     MASK_TBL_ENTRY(0,            0),      // 009  RSV
00567     MASK_TBL_ENTRY(0,            0),      // 010  RSV
00568     MASK_TBL_ENTRY(0,            0),      // 011  RSV
00569     MASK_TBL_ENTRY(0,            0),      // 012  RSV
00570     MASK_TBL_ENTRY(0,            0),      // 013  RSV
00571     MASK_TBL_ENTRY(0,            0),      // 014  RSV
00572     MASK_TBL_ENTRY(0,            0),      // 015  RSV
00573     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(0)), // 016  IRQ 0
00574     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(1)), // 017  IRQ 1
00575     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(2)), // 018  IRQ 2
00576     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(3)), // 019  IRQ 3
00577     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(4)), // 020  IRQ 4
00578     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(5)), // 021  IRQ 5
00579     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(0)), // 022  IRQ 6
00580     MASK_TBL_ENTRY(CYGARC_IERL,  BIT(0)), // 023  IRQ 7
00581     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(0)), // 024  IRQ 8
00582     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(1)), // 025  IRQ 9
00583     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(2)), // 026  IRQ 10
00584     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(3)), // 027  IRQ 11
00585     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(4)), // 028  IRQ 12
00586     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(5)), // 029  IRQ 13
00587     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(6)), // 030  IRQ 14
00588     MASK_TBL_ENTRY(CYGARC_IERH,  BIT(7)), // 031  IRQ 15
00589 
00590     //---------------------------------------------------------------------------------
00591     //
00592     //
00593     MASK_TBL_ENTRY(NO_MASK_REG,  0),      // 032  SWDTEND
00594     MASK_TBL_ENTRY(CYGARC_TCSRW, BIT(5)), // 033  WOVI
00595     MASK_TBL_ENTRY(0,            0),      // 034  RSV
00596     MASK_TBL_ENTRY(CYGARC_REFCRH,BIT(6)), // 035  CMI
00597     MASK_TBL_ENTRY(0,            0),      // 036  RSV
00598     MASK_TBL_ENTRY(0,            0),      // 037  RSV
00599     MASK_TBL_ENTRY(CYGARC_ADCSR, BIT(6)), // 038  ADI
00600     MASK_TBL_ENTRY(0,            0),      // 039  RSV
00601     
00602     //---------------------------------------------------------------------------------
00603     // TPU 0
00604     //
00605     MASK_TBL_ENTRY(CYGARC_TIER0, BIT(0)), // 040  TGI0A
00606     MASK_TBL_ENTRY(CYGARC_TIER0, BIT(1)), // 041  TGI0B
00607     MASK_TBL_ENTRY(CYGARC_TIER0, BIT(2)), // 042  TGI0C
00608     MASK_TBL_ENTRY(CYGARC_TIER0, BIT(3)), // 043  TGI0D
00609     MASK_TBL_ENTRY(CYGARC_TIER0, BIT(4)), // 044  TCI0V
00610     MASK_TBL_ENTRY(0,            0),      // 045  RSV
00611     MASK_TBL_ENTRY(0,            0),      // 046  RSV
00612     MASK_TBL_ENTRY(0,            0),      // 047  RSV
00613 
00614     //---------------------------------------------------------------------------------
00615     // TPU 1
00616     //
00617     MASK_TBL_ENTRY(CYGARC_TIER1, BIT(0)), // 048  TGI1A
00618     MASK_TBL_ENTRY(CYGARC_TIER1, BIT(1)), // 049  TGI1B
00619     MASK_TBL_ENTRY(CYGARC_TIER1, BIT(4)), // 050  TCI1V
00620     MASK_TBL_ENTRY(CYGARC_TIER1, BIT(5)), // 051  TCI1U
00621     
00622     //---------------------------------------------------------------------------------
00623     // TPU 2
00624     //
00625     MASK_TBL_ENTRY(CYGARC_TIER2, BIT(0)), // 052  TGI2A
00626     MASK_TBL_ENTRY(CYGARC_TIER2, BIT(1)), // 053  TGI2B
00627     MASK_TBL_ENTRY(CYGARC_TIER2, BIT(4)), // 054  TCI2V
00628     MASK_TBL_ENTRY(CYGARC_TIER2, BIT(5)), // 055  TCI2U
00629     
00630     //---------------------------------------------------------------------------------
00631     // TPU 3
00632     //
00633     MASK_TBL_ENTRY(CYGARC_TIER3, BIT(0)), // 056  TGI3A
00634     MASK_TBL_ENTRY(CYGARC_TIER3, BIT(1)), // 057  TGI3B
00635     MASK_TBL_ENTRY(CYGARC_TIER3, BIT(2)), // 058  TGI3C
00636     MASK_TBL_ENTRY(CYGARC_TIER3, BIT(3)), // 059  TGI3D
00637     MASK_TBL_ENTRY(CYGARC_TIER3, BIT(4)), // 060  TCI3V
00638     MASK_TBL_ENTRY(0,            0),      // 061  RSV
00639     MASK_TBL_ENTRY(0,            0),      // 062  RSV
00640     MASK_TBL_ENTRY(0,            0),      // 063  RSV
00641     
00642     //---------------------------------------------------------------------------------
00643     // TPU 4
00644     //
00645     MASK_TBL_ENTRY(CYGARC_TIER4, BIT(0)), // 064  TGI4A 
00646     MASK_TBL_ENTRY(CYGARC_TIER4, BIT(1)), // 065  TGI4B
00647     MASK_TBL_ENTRY(CYGARC_TIER4, BIT(4)), // 066  TCI4V
00648     MASK_TBL_ENTRY(CYGARC_TIER4, BIT(5)), // 067  TCI4U
00649 
00650     //---------------------------------------------------------------------------------
00651     // TPU 5
00652     //
00653     MASK_TBL_ENTRY(CYGARC_TIER5, BIT(0)), // 068  TGI5A
00654     MASK_TBL_ENTRY(CYGARC_TIER5, BIT(1)), // 069  TGI5B
00655     MASK_TBL_ENTRY(CYGARC_TIER5, BIT(4)), // 070  TCI5V
00656     MASK_TBL_ENTRY(CYGARC_TIER5, BIT(5)), // 071  TCI5U
00657     
00658     //---------------------------------------------------------------------------------
00659     // TMR 0
00660     //
00661     MASK_TBL_ENTRY(CYGARC_8TCR0, BIT(6)), // 072  CMIA0
00662     MASK_TBL_ENTRY(CYGARC_8TCR0, BIT(7)), // 073  CMIB0
00663     MASK_TBL_ENTRY(CYGARC_8TCR0, BIT(5)), // 074  OVI0
00664     MASK_TBL_ENTRY(0,            0),      // 075  RSV
00665     
00666     //---------------------------------------------------------------------------------
00667     // TMR 1
00668     //
00669     MASK_TBL_ENTRY(CYGARC_8TCR1, BIT(6)), // 076  CMIA1
00670     MASK_TBL_ENTRY(CYGARC_8TCR1, BIT(7)), // 077  CMIB1
00671     MASK_TBL_ENTRY(CYGARC_8TCR1, BIT(5)), // 078  OVI1
00672     MASK_TBL_ENTRY(0,            0),      // 079  RSV
00673     
00674     //---------------------------------------------------------------------------------
00675     // DMAC
00676     //
00677     MASK_TBL_ENTRY(CYGARC_DMABCRL, BIT(0)), // 080  DMTEND0A
00678     MASK_TBL_ENTRY(CYGARC_DMABCRL, BIT(1)), // 081  DMTEND0B
00679     MASK_TBL_ENTRY(CYGARC_DMABCRL, BIT(2)), // 082  DMTEND1A
00680     MASK_TBL_ENTRY(CYGARC_DMABCRL, BIT(3)), // 083  DMTEND1B
00681     
00682     //---------------------------------------------------------------------------------
00683     // EXDMAC
00684     //
00685     MASK_TBL_ENTRY(CYGARC_EDMDR0L, BIT(7)), // 084  EXDMTEND0A
00686     MASK_TBL_ENTRY(CYGARC_EDMDR1L, BIT(7)), // 085  EXDMTEND0B
00687     MASK_TBL_ENTRY(CYGARC_EDMDR2L, BIT(7)), // 086  EXDMTEND1A
00688     MASK_TBL_ENTRY(CYGARC_EDMDR3L, BIT(7)), // 087  EXDMTEND1B
00689 
00690     //---------------------------------------------------------------------------------
00691     // SCI 0
00692     //
00693     MASK_TBL_ENTRY(CYGARC_SCR0,  BIT(6)), // 088  ERI0
00694     MASK_TBL_ENTRY(CYGARC_SCR0,  BIT(6)), // 089  RXI0
00695     MASK_TBL_ENTRY(CYGARC_SCR0,  BIT(7)), // 090  TXI0
00696     MASK_TBL_ENTRY(CYGARC_SCR0,  BIT(2)), // 091  TEI0
00697 
00698     //---------------------------------------------------------------------------------
00699     // SCI 1
00700     //
00701     MASK_TBL_ENTRY(CYGARC_SCR1,  BIT(6)), // 092  ERI1
00702     MASK_TBL_ENTRY(CYGARC_SCR1,  BIT(6)), // 093  RXI1
00703     MASK_TBL_ENTRY(CYGARC_SCR1,  BIT(7)), // 094  TXI1
00704     MASK_TBL_ENTRY(CYGARC_SCR1,  BIT(2)), // 095  TEI1
00705 
00706     //---------------------------------------------------------------------------------
00707     // SCI 2
00708     //
00709     MASK_TBL_ENTRY(CYGARC_SCR2,  BIT(6)), // 096  ERI2
00710     MASK_TBL_ENTRY(CYGARC_SCR2,  BIT(6)), // 097  RXI2
00711     MASK_TBL_ENTRY(CYGARC_SCR2,  BIT(7)), // 098  TXI2
00712     MASK_TBL_ENTRY(CYGARC_SCR2,  BIT(2))  // 099  TEI2
00713 };
00714 
00715 
00716 //==========================================================================
00717 //                          SET INTERRUPT PRIORITY
00723 //==========================================================================
00724 void hal_interrupt_set_level(int vector, int level)
00725 {
00726     cyg_uint32               prio_reg;
00727     cyg_uint16               prio_data;
00728     cyg_uint16               mask;
00729     int_prio_conf_t         *pint_regs;             // points to interrupt config structure
00730     static const cyg_uint16  prio_grp_mask_tbl[4] =
00731     {
00732         0x0007, 0x0070, 0x0700, 0x7000 
00733     };
00734 
00735     
00736     if (CYGNUM_HAL_INTERRUPT_NMI == vector)
00737     {
00738         return;
00739     }
00740     //
00741     // We do not check vector ranges with assertions here because
00742     // this is already done in cyg_interrupt_mask and the user should
00743     // not call this funcion directly. But we check priority because
00744     // cyg_interrupt_set_level does not know about H8S priotity ranges
00745     //
00746     CYG_ASSERT(CYGNUM_HAL_INT_PRIO_LOWEST <= level 
00747             && CYGNUM_HAL_INT_PRIO_HIGHEST >= level, "invalid interrupt priority level" );
00748     
00749     pint_regs = (int_prio_conf_t *)&hal_int_prio_conf_tbl[vector];  // get pointer to configuration data
00750     prio_reg = hal_prio_reg_tbl[pint_regs->prio_reg_no];            // get priority register 
00751     
00752     //
00753     //  check if this interrupt vector really supports priority settings
00754     //
00755     CYG_ASSERT(prio_reg != 0, "This interrupt doesn't support priority settings");
00756     
00757     //
00758     // now set up the selected priority
00759     //
00760     HAL_READ_UINT16(prio_reg, prio_data);                      // read value from priority register
00761     mask = prio_grp_mask_tbl[pint_regs->prio_bit_group];       // create mask
00762     prio_data &= ~mask;                                        // clear priority to zero
00763     prio_data |= (level << (pint_regs->prio_bit_group << 2));  // set new priority
00764     HAL_WRITE_UINT16(prio_reg, prio_data);                     // write priority back into priority register
00765     
00766     //
00767     // we store the priority settings in the hal_int_prio_tbl[] for
00768     // fast access from vectors.asm
00769     //
00770     hal_int_prio_tbl[vector] = level;
00771 }
00772 
00773 
00774 //==========================================================================
00775 //                      SET INTERRUPT DETECTION MODE
00789 //==========================================================================
00790 void hal_interrupt_configure(int vector, int level, int up)
00791 {
00792     #define INT_REQ_LEVEL_LOW    0x00
00793     #define INT_REQ_EDGE_FALLING 0x01
00794     #define INT_REQ_EDGE_RISING  0x10
00795     #define INT_REQ_EDGE_BOTH    0x11
00796     cyg_uint16  reg_data;           // temprorary stores register data
00797     cyg_uint16  mask;               // required for masking
00798     cyg_uint32  iscr;               // interrupt sense control register address
00799     cyg_uint8   index;              // index into interrupt configuration table
00800     cyg_uint8   int_req_conf;       // contains configuration data to be written into iscr
00801 
00802     
00803     //
00804     // Check if vector, level and up are valid values
00805     //
00806     HAL_TRANSLATE_VECTOR(vector, index);
00807     CYG_ASSERT(!(up && level), "Cannot trigger on high level!"); 
00808     CYG_ASSERT((CYGNUM_HAL_INTERRUPT_EXTERNAL_0  <= vector 
00809              && CYGNUM_HAL_INTERRUPT_EXTERNAL_15 >= vector) 
00810              || CYGNUM_HAL_INTERRUPT_NMI, "only external interrupts and NMI are configurable" );
00811     CYG_ASSERT(!(level && (vector == CYGNUM_HAL_INTERRUPT_NMI)), "NMI cannot trigger on level - only rising or falling edge");
00812     //
00813     // NMI interrupt needs special treatment - only rising or falling edge
00814     // is configurable for NMI
00815     //
00816     if (CYGNUM_HAL_INTERRUPT_NMI == vector)
00817     {
00818         HAL_READ_UINT8(CYGARC_INTCR, reg_data);
00819         if (up)
00820         {
00821             reg_data |= CYGARC_INTCR_NMIEG_RIS;
00822         }
00823         else
00824         {
00825             reg_data &= ~CYGARC_INTCR_NMIEG_RIS;
00826         }
00827         HAL_WRITE_UINT8(CYGARC_INTCR, reg_data);
00828         
00829         return;
00830     }
00831     //
00832     // if it is not NMI then we are here and it is an external interrupt
00833     //
00834     int_req_conf = INT_REQ_EDGE_FALLING;
00835     if (level) 
00836     {    
00837         int_req_conf = INT_REQ_LEVEL_LOW;
00838     }
00839     if (up) 
00840     {
00841         int_req_conf = INT_REQ_EDGE_RISING;
00842     }
00843     //
00844     // decide if we need ISCRL or ISCRH
00845     //
00846     iscr = (vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_7) ? CYGARC_ISCRL : CYGARC_ISCRH;
00847     mask = 3 << ((vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0) & 7) * 2;
00848     //
00849     // Read value, write new configuration data and store value back into
00850     // iscr register
00851     //
00852     HAL_READ_UINT16(iscr, reg_data);
00853     reg_data &= ~mask;
00854     reg_data |= int_req_conf << (((vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0) & 7) << 1);
00855     HAL_WRITE_UINT16(iscr, reg_data);
00856 }
00857 
00858 
00859 //==========================================================================
00860 //                           ATTACH ISR TO VECTOR
00876 //==========================================================================
00877 void hal_interrupt_attach(int vector, CYG_ADDRESS isr, CYG_ADDRWORD data, CYG_ADDRESS object)
00878 {
00879     cyg_uint32 index;  
00880     
00881                    
00882     HAL_TRANSLATE_VECTOR(vector, index);   
00883                                      
00884     //
00885     // If the user disabled the watchdog timer overflow code then we check
00886     // here, if user tries to use this vector. Set_level is called each time
00887     // an interrupt vector is attached.
00888     //
00889 #if !defined(CYGBLD_HAL_H8S_WATCHDOG_INTERRUPT_CODE)
00890     CYG_ASSERT(CYGNUM_HAL_INTERRUPT_WOVI != vector, "Watchdog timer overflow interrupt code not supported" );
00891 #endif  
00892 
00893     CYG_ASSERT(hal_int_mask_tbl[index].address != 0, "H8S interrupt vector not supported");
00894     //
00895     // now attach the interrupt data if the vector is free
00896     //                                                                         
00897     if (hal_interrupt_handlers[index] == (CYG_ADDRESS)HAL_DEFAULT_ISR)        
00898     {                                                                          
00899         hal_interrupt_handlers[index] = (CYG_ADDRESS)isr;                   
00900         hal_interrupt_data[index]     = (CYG_ADDRWORD)data;                 
00901         hal_interrupt_objects[index]  = (CYG_ADDRESS)object;                
00902     }  
00903 }
00904 
00905 
00906 //==========================================================================
00907 //                                HARDWARE RESET
00912 //==========================================================================
00913 #ifndef CYGPKG_HAL_H8S_WDRESET_DEFINED
00914 void h8s_reset_watchdog(void)
00915 {
00916     cyg_uint8 tmp;
00917     
00918     
00919     //
00920     // Dummy read to reset OVF bit
00921     //
00922     HAL_READ_UINT8(CYGARC_TCSRR, tmp);
00923     tmp &= ~CYGARC_TCSR_OVF;
00924     tmp |= CYGARC_TCSR_WT;
00925     //
00926     // Setup timer as watchdog timer with clock/2 and clear overflow flag
00927     //
00928     HAL_WRITE_UINT16(CYGARC_TCSRW, tmp | CYGARC_TCSR_MAGIC);
00929     //
00930     // enable reset if timer overflows
00931     //
00932     HAL_WRITE_UINT8(CYGARC_RSTCSRR, tmp);
00933     tmp |= CYGARC_RSTCSR_RSTE;                   
00934     HAL_WRITE_UINT16(CYGARC_RSTCSRW, tmp | CYGARC_RSTCSR_DATA_MAGIC);
00935     //
00936     // setup timer up counter register
00937     //
00938     HAL_WRITE_UINT16(CYGARC_TCNTW, 0x80 | CYGARC_TCNT_MAGIC);
00939     //
00940     //
00941     // start timer - Set Timer Enable bit in TCSR
00942     //
00943     HAL_READ_UINT8(CYGARC_TCSRR, tmp);
00944     tmp |= CYGARC_TCSR_TME;
00945     HAL_WRITE_UINT16(CYGARC_TCSRW, tmp | CYGARC_TCSR_MAGIC);
00946     //
00947     // loop untill h8s resets
00948     //
00949     while (1)
00950     {
00951         // do nothing
00952     }
00953 }
00954 #endif
00955 //------------------------------------------------------------------------
00956 // End of var_misc.c
Generated on Tue Feb 17 09:06:13 2004 for eCos EDOSK-2674 HAL by doxygen 1.3.5